Implementación de un servidor web para gesitonar un core time-to-digital-converter multicanal empleado en sistemas médicos PET

This contribution describes the development and implementation of a high resolution system based on a Core Time-to-Digital Converter (TDC) for the improvement of medical images. This system is able to obtain temporary differences for multiple simultaneous channels, with the aim of improving one of the technologies that has most prospered in recent years in the field of nuclear medicine. This medical area has advanced significantly in recent years due to the contribution that technology has provided in terms of improving resolution in the systems used. One of the techniques that has advanced the most in this field has been Positron Emission Tomography (PET), based on a medical technique by which images of the spatial and temporal distribution of metabolic processes generated inside are obtained. of the organism.

The TDC that is presented is able to obtain a resolution lower than 100 ps, ​​which is the necessary to obtain an appreciable improvement in the image quality of the current PET. For this purpose, the internal structure of the last families of the electronic Field-Programmable Gate Array (FPGA) devices based on carry logic and a strict calibration process has been used. Likewise, the suitability of the use of the TDC in PET medical systems is demonstrated, offering the possibility of determining the Time of Flight (TOF). A technique that incorporates few PETs in the market due to its complexity, and that brings multiple advantages such as increased accuracy in the detection of neoplasms, better reconstruction of the image and reduction of the patient's exposure time to radiopharmaceuticals that are introduced in your body.
In attention to the exposed problems, the system to be implemented will be able to detect events with a temporal resolution much lower than the frequency of the system clock, perform the management of the data obtained through a software microprocessor embedded in the FPGA and provide a representation graphic of them.

This graphic representation can be done at the local level, using a low-data rate serial communication, and remotely through a web application that communicates with the system through a high-speed remote management communication.