Publicado en 3C Tecnología. Special Issue – March 2020

Autores

• G. Karthy
• P. Sivakumar

Resumen

Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM, ROM, DRAM, etc., are the different types of memory and it becomes difficult to test the memory because of the complexity of the design increases day by day. The testing of memory is very difficult as it’s required many test patterns. In this paper, a new test architecture is designed using a response analyzer and checker to detect a fault on a chip, and the modified MARCH C algorithm is also proposed to check the fault in the memory in the shortest time.

Artículo

Palabras clave

RAM, SOC, Response analyzer, Checker, March algorithm.

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