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DESIGN OF MODIFIED MARCH-C ALGORITHM AND
BUILT-IN SELF-TEST ARCHITECTURE FOR MEMORIES
G. Karthy
B.E., M. Tech., Assistant Professor, ECE,
Kalasalingam Academy of research and education.
Krishnankoil, (India).
E-mail: g.karthy@klu.ac.in ORCID: https://orcid.org/0000-0003-0084-4185
P. Sivakumar
B.E., M.Tech., Ph.D., Professor, ECE,
Kalasalingam Academy of Research and Education.
Krishnankoil, (India).
E-mail: siva@klu.ac.in ORCID: https://orcid.org/0000-0003-1328-8093
Recepción:
05/12/2019
Aceptación:
30/12/2019
Publicación:
23/03/2020
Citación sugerida:
Karthy, G., y Sivakumar, P. (2020). Design of Modied March-C Algorithm and Built-in self-test
architecture for Memories. 3C Tecnología. Glosas de innovación aplicadas a la pyme. Edición Especial, Marzo
2020, 219-229. http://doi.org/10.17993/3ctecno.2020.specialissue4.219-229
Suggested citation:
Karthy, G., & Sivakumar, P. (2020). Design of Modied March-C Algorithm and Built-in self-test
architecture for Memories. 3C Tecnología. Glosas de innovación aplicadas a la pyme. Edición Especial, Marzo
2020, 219-229. http://doi.org/10.17993/3ctecno.2020.specialissue4.219-229
220 http://doi.org/10.17993/3ctecno.2020.specialissue4.219-229
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254 – 4143 Edición Especial Special Issue Marzo 2020
ABSTRACT
Semiconductor Memories is a pivotal aspect as its technology growth increases. RAM,
ROM, DRAM, etc., are the dierent types of memory and it becomes dicult to test
the memory because of the complexity of the design increases day by day. The testing
of memory is very dicult as it’s required many test patterns. In this paper, a new test
architecture is designed using a response analyzer and checker to detect a fault on a chip,
and the modied MARCH C algorithm is also proposed to check the fault in the memory
in the shortest time.
KEYWORDS
RAM, SOC, Response analyzer, Checker, March algorithm.
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1. INTRODUCTION
Testing the complete memory is a dicult task. Testing can be done with help of fault
models in the Built-in self-test (BIST) architecture. Many fault models are available to test
the memory. Here we have used traditional faults models to test the memory. Out of various
available algorithms MARACH algorithms provides better fault detection and coverage. In
this paper, we proposed a new architecture that consists of the checker, response analyzer,
memory unit and a BIST controller with Modied March C algorithm. By using a checker,
we can get more précised output.
2. PROBLEM STATEMENT
Memory testing is used to identify that the memory is capable of writing and reading the
correct data or not. March based algorithms can identify and locating the fault types which
can help to check the design and manufacturing errors. The quality of the test is strongly
dependent on the fault model in terms of its fault coverage, its test length as well as the test
time required.
In this paper Modied MARCH C- the algorithm is implemented to detects the maximum
fault. In addition to that Response analyzer and Checker are included in this architecture
to identies more faults with high precision.
3. TYPES OF FAULT IN THE MEMORY
There are 3 types functional faults models involved in the memory:
1. Memory cell faults.
2. Address Decoder faults.
3. Dynamic faults.
3.1. MEMORY CELL FAULTS
This type of faults forces the contents from 0 to 1 or does not change the contents. Types are
SAF- Stuck at fault, SOF-Stuck at open fault, TF – Transition fault, DRF-Data retention
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fault, CF- Coupling fault, BF-Bridging fault BF, NPSF-Neighborhood Pattern Sensitive
Fault, Active (Dynamic) NPSF, Passive NPSF, Static NPSF.
3.2. ADDRESS DECODER FAULTS (AFs)
It occurs in the address, it can be:
Cell not accessed by an address, many cells are accessed by an address, cell accessed by
many addresses.
3.3. DYNAMIC FAULTS
1. Recovery faults: Part of the memory cannot recover fast enough from a previous state.
2. Disturb faults: victim cell forced to 1 or 0 when we read or write aggressor cell (maybe
the same cell).
3. Data Retention faults: Because memory loses its content spontaneously, data cannot be
retrieved.
4. MARCH ALGORITHMS
The xed sequence of read/write operations is carried out to check whether the memory
cell is good. The targeted fault model decides the real number of write/read operations
and the order of the operations. March tests are the most commonly used memory test
algorithms, in which there are xed sequences of March elements. Then March element
is applied to a cell in memory one by one. The operation can be in either descending or
ascending address order. The notations of the March algorithm are summarized below:
↑: address sequence changes in ascending order
↓: address sequence changes in descending order
↕: address sequence can change either way
R0: read operation (reading a 0 from a cell)
R1: read operation (reading a 1 from a cell)
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W0: write operation (writing a 0 to a cell)
W1: write operation (writing a 1 to a cell)
The response will be 0 or 1 if the test algorithm reads a cell, and they are specied as R0
and R1, respectively. Similarly, writing a 1 into a cell is denoted as W1 and writing 0 as W0.
A March- based test algorithm is a xed sequence of read and write operations called
March element. It is specied by a number of reads and write operations and n address
order. MATS, MATS+, March-C, March-Y, March-A, and March-B are dierent types of
March- based tests. Because of its simplicity and high fault coverage in most contemporary
memory BIST, March based test algorithm is implemented because of its high fault coverage
and simplicity. The various March algorithms and Features are stated in the below table:
Table 1. Memory Algorithms and its features.
Sl. No
Type of the March
algorithm
Features
1. MARCHING 1/0 Test
It can detect Auxiliary faults (AF) and Stuck at faults (SAF) and Transition faults
(TF).
2. MATS Test Modied Algorithmic Test Sequence, it can detect OR type technology.
3. MATS+ Test It can detect all Stuck at faults (SAF) and Auxiliary faults (AF).
4. MATS++ It is like MAT+ additionally it covers transition faults (TF).
5. MARCH X
It can detect all stuck at faults, auxiliary faults, transition faults and Coupling
faults
6. MARCH C
It can also detect all stuck at fault, auxiliary faults, transition faults and Coupling
faults
7. MARCH C- Redundancy of MARCH C algorithm is removed.
8. MARCH A
It can detect AF’s, SAF’s, linked Coupling Fault CFid’s, TF’s and certain CFin’s
linked with CFid’s
9. MARCH Y Extended version of MARCH X
10. MARCH B Extended version of MARCH A
5. BUIILT -IN-SELF-TEST(BIST)
Built-In Self-Test (BIST), test generation and response evaluation hardware are included
on-chip so that in-circuit tests can be performed with minimal need for external test
equipment, if any. The BIST technique is a common technique to test memories (RAM
and ROMs).
There are two types of BIST; On-line BIST and O-line BIST.
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a. On-line BIST: It is implemented on the chip itself. It has area overhead but has the
shortest test time.
b. O-line BIST: It is implemented o the chip itself. It has no area overhead but has
the longest test time.
6. TEST ARCHITECTURE
Response Analyzer Checker
Memory
Under Test
BIST Controller
data
Err Signal
add
e
r
r
data
w/r
add
O/P data
r
e
f
a
d
d
d
a
t
a
c
n
t
Figure 1. BIST Architecture.
7. EXPLANATION AND RESULTS
Built-In Self-Test (BIST), test generation and response evaluation hardware are included
on-chip so that in-circuit tests can be performed with minimal need for external test
equipment, if any. The BIST technique is a common technique to test memories (RAM
and ROMs).
This architecture consists of BIST Controller, Memory Under Test (MUT), Checker and
Response Analyzer. Clock signal becomes to enable the BIST controller to starts working.
The BIST controller gives the control signal to the memory. Then the memory undergoes
read or/write operation according to the March algorithm.
Then the output from the memory is given to the checker. The checker compares the
output from the memory to the data stored inside it. Whenever the fault occurs the checker
gives the error signal, the original data along with the address to the response analyzer.
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The response analyzer is used to switch the controller from normal to repair mode. Whenever
the repair mode becomes to enable the controller automatically enables the write signal to
repair the fault according to the address and data given by the response analyzer. After
the repair operation gets completed the ref signal becomes enable to indicate that fault is
repaired. As the continue signal becomes to enable the controller switches to normal mode.
This process is continued until the end of the operation. The export mask address signal is
used to indicate whether the fault is repairable or not. In this way, this test architecture is
used to test and repair the fault in memory with maximum accuracy.
Figure 2. Data writing an operation into the memory and checker.
Figure 3. Data reading operation from the memory and it is compared inside the checker for error.
Figure 4. Reading, Writing, and comparison of the data inside the checker for detecting the error.
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8. CONCLUSION
MARCH tests are extensively being used today for functional testing of memory technologies.
They are more ecient with better fault coverage than the older classical pattern. In this
project modied MARCH C Algorithm with modied BIST architecture are proposed.
With this simple BIST architecture and modied MARCH C, testing time can be reduced
because two read/write operations carried out in a single clock time. So, Testing Speed can
also be doubled. It also provides better fault coverage as MARCH C algorithm covers most
of the faults in the memory.
ACKNOWLEDGMENT
We thank the ECE department of Kalasalingam Academy of Research and education,
Krishnankoil for supporting this research by providing their center for VLSI lab facility.
The Facility which is sponsored by Department of Science and technology (DST) under
Fund for Improvement of S&T Infrastructure (FIST) Scheme.
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