Thermal and congestion aware algorithm for 3D integrated circuits

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Publicado en 3C Tecnología. Edición Especial/Special Issue – Noviembre/November 2021



In VLSI physical Design methodology, Routing has been a most important in VLSI design, because the routing results are like circuit delay, power consumption, chip responsibility and manufacturability etc. With the advancements in 3D ICs, this issue has turned out to be substantially more complex. With the size of present-day plans at a huge number of nets, global routing has turned into a noteworthy computational test. The main purpose of the global routing is to reduce the wire length. In this work, a thermal and congestion aware formula is projected to attenuate the mixture wire length and to beat the congestion by systematically diffusive the nets within the routing region. The investigational output of the planned global router utilizes less wirelength and keeps far from congestion by ripping up and re-routing the nets. In future planned to use machine learning algorithm to reduce temperature between the layers in an integrated circuit.


Palabras clave

Global Routing, NP completeness, 3D ICs, Wire Length Minimization, Congestion.

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