Design of reconfigurable MEMS-PLL for high end turning circuits

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Publicado en 3C Tecnología. Edición Especial/Special Issue – Noviembre/November 2021



The designs of memristive circuits become more demanding since the evaluation of miniaturized models are rapidly increasing every year. Here a novel Memristive Digital Phase locked loop circuit is evaluated. In the existing research works it is found that design of analog domain memristor creates enormous noise and limitations. In the Proposed system, Design of MEMS activated DPLL is evaluated. Digital PLL plays a major role in high-speed communication platforms. The benefits of PLL like jitter free clock generation, stabilized regulation and less resilient is improved even more in MEMS controlled DPLL we call as MEMPLL. In the proposed system an adaptive DPLL vary with respect to Memristor is developed here. The evaluation of memristor emerging in the field of large memory architecture and complex tuning. The advantage of storing the N info at the memristor can vary the development circuits in a reconfigurable manner. Here, the parameters are compared by DCO and ADC method and the power is achieved by 3.0 mw.


Palabras clave

Memristor, DPLL, Reconfigurable Design, Low power RTL, Clock gating.

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