Publicado en 3C Tecnología. Edición Especial/Special Issue – Noviembre/November 2021
Reversible logic is leading area in power consumption. Based on its application, its emerging trend in power consumption. In ideal situations, reversible circuit yield nil power. Different methods of multiplier optimized in this paper. Like quantum computers, multipliers required to develop computational units. In the paper, two different methods of multiplier developed with very large bit width. Based on partial products hierarchical method is developed. Another method is Karatsuba’s algorithm developed based on divide and conquers method. Finally, we compare the results of both two methods. The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware. In nanotechnology applications this multiplier can be used to construct complex system.
Palabras claveKaratsuba’s algorithm, Hierarchical method, FFT, Reversible gates.
- Improved result of TSV and Slew aware 3D Gated Clock Tree Synthesis using charge recycling configuration
- Hybrid technique for improving underwater image
- An efficient Hybrid Active Power Filter (H-APF) for harmonic mitigation using compensation techniques
- IoT based vital signs monitoring system for human beings
- ADHAAR: A reliable Data Hiding techniques with (NNP2) Algorithmic Approach using X-ray images
- Identification of drivers drowsiness based on features extracted from EEG signal using SVM classifier
- A compact ultra-wide band patch antenna using defected ground structure
- Design of reconfigurable MEMS-PLL for high end turning circuits
- Energy efficient design of EHF-5G antennas with enhanced bandwidth for navigation satellite applications
- Encrypted fusion of face and iris biometrics