Optimization of multiplier in reversible logic

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Publicado en 3C Tecnología. Edición Especial/Special Issue – Noviembre/November 2021



Reversible logic is leading area in power consumption. Based on its application, its emerging trend in power consumption. In ideal situations, reversible circuit yield nil power. Different methods of multiplier optimized in this paper. Like quantum computers, multipliers required to develop computational units. In the paper, two different methods of multiplier developed with very large bit width. Based on partial products hierarchical method is developed. Another method is Karatsuba’s algorithm developed based on divide and conquers method. Finally, we compare the results of both two methods. The projected reversible multipliers are enhanced in terms of quantum cost, number of constant inputs, number of garbage outputs and complexity in hardware. In nanotechnology applications this multiplier can be used to construct complex system.


Palabras clave

Karatsuba’s algorithm, Hierarchical method, FFT, Reversible gates.

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