In physical design of Integrated Circuits (ICs) especially after placement, Clock Tree Synthesis (CTS) plays a major part in the general chip efficiency. Three Dimensional Integrated Circuits (3D ICs) based on Through Silicon Via (TSV) present a major challenge for IC developers. 3D gated CTS on the TSV-TSV coupling model is an effective approach to reduce power, delay and clock skew. This paper proposes a slew aware TSV arrangement with clock gating logic in 3D CTS. It consists of the following 3 phases, viz., TSV clock tree synthesis, gated logic insertion in 3D CTS and charge recycling configuration for power gating structures. Unlike the previous methods available in literature, the proposed TSV aware 3D clock tree synthesis performs with TSV model in the beginning followed by the gated logic. Multiple experiments were conducted on the bench mark circuits and it can be inferred that, compared with the existing 3D CTS method on TSV-TSV coupling model, the proposed 3D gated CTS method on TSV model is simple and efficient for practical applications achieving average reduction in the clock skew and power.