ENERGY EFFICIENT AND HIGH–
PERFORMANCE FIR FILTER DESIGN ON
SPARTAN–6 FPGA
Bishwajeet Pandey
Gyancity Research Lab, Motihari. Thapar University. India (India)
E–mail: gyancity@gyancity.com
Abhishek Jain
Thapar Uiversity, Sungkyunkwan University (South Korea)
E–mail: abhishek.jain@thapar.edu
Abhishek Kumar
Motihari. Thapar University. India (India)
E–mail: abhishek@gyancity.com
Pervesh Kumar
Sungkyunkwan University (South Korea)
E–mail: itspervesh@skku.edu
Akbar Hussain
Aalborg University (Denmark)
E–mail: akh@et.aau.dk
Jason Levy
University of Hawaii (USA)
E–mail: jlevy@hawaii.edu
Bhawani Shankar Chowdhry
Mehran University of Science and Technology. Sindh (Pakistan)
E–mail: bhawani.chowdhry@faculty.muet.edu.pk
Recepción: 05/03/2019 Aceptación: 27/03/2019 Publicación: 17/05/2019
Citación sugerida:
Pandey, B., Jain, A., Kumar, P., Hussain, A., Levy, J. y Chowdhry, B. S. (2019). Energy
Ecient and High–Performance FIR Filter Design on Spartan–6 FPGA. 3C Tecnología.
Glosas de innovación aplicadas a la pyme. Edición Especial, Mayo 2019, pp. 36–49. doi: http://
dx.doi.org/10.17993/3ctecno.2019.specialissue2.36–49
Suggested citation:
Pandey, B., Jain, A., Kumar, P., Hussain, A., Levy, J. & Chowdhry, B. S. (2019). Energy
Ecient and High–Performance FIR Filter Design on Spartan–6 FPGA. 3C Tecnología.
Glosas de innovación aplicadas a la pyme. Special Issue, May 2019, pp. 36–49. doi: http://dx.doi.
org/10.17993/3ctecno.2019.specialissue2.36–49
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
38
ABSTRACT
In this paper, we are going to design the energy ecient Gaussian low pass
FIR lter on spartan–6 FPGA. To make an energy ecient lter, we have used
dierent methods in this paper like capacitance scaling, frequency scaling, and
then we analysed the demand for power by Gaussian low pass FIR lter. The
frequency range which is used in this paper is 1 GHz, 2GHz, 2.5GHz, 5 GHz,
10 GHz and the range of capacitance which we have used in this paper is 5pF,
10pF, 25pF, 40pF and 50 pF. An FIR lter always remnants in linear phase with
the help of symmetric coecient and this is the very useful feature of the FIR
lter for phase sensitive application like data communications etc. At present,
there are many dierent methods of communications and networking. So, in this
paper, we have designed an energy–ecient FIR lter and that design will faster
than traditional design.
KEYWORDS
FIR lter, Gaussian, FPGA, Energy ecient, Spartan–6 FPGA.
39
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
39
1. INTRODUCTION
Gaussian lter is a type of lter and the impulse response of this lter is in
Gaussian function. A linear phase is the important feature of any lter. Linear
phase means that the lter phase response of the lter will be a linear function of
frequency. A nite impulse response (FIR) is a lter and it settles to zero in nite
time so then impulse response, and that features make the FIR an ideal choice for
phase sensitive application i.e. data communications, seismology, crossover lters
and mastering etc. Here we can say that an energy ecient design of FIR lter
leads to energy ecient data communication.
Figure 1. Top Level Schematic of Gaussian Low Pass FIR Filter.
Spartan–6 FPGA is a high–performance FPGA in terms of price and performance
using 45nm transistor technology. The function of the low pass lter is to pass the
low–frequency signals and prohibits the signals which are higher than the cut–o
frequency as shown in Figure 1. In this paper, we have operated the Gaussian
low pass lter with 1GHz, 2GHz, 2.5GHz, 5GHz, and maximum of 10 GHz
frequency. We have also used capacitance scaling method to analyse the power
(Pandey, Kumar, Das, Yadav & Pandey, 2014).
2. LITERATURE SURVEY
In Pandey, et al. (2014), the author has used capacitance scaling techniques as well
as frequency scaling techniques but on 28nm Kintex–7 FPGA using available
240 DSP slice. There is open scope to design dierent energy ecient DSP
IP block like Modulation, Transforms, Tring functions, Demodulation, Error
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
40
Correction. In this paper, the dynamic power of the CMOS circuit is dependent
on the capacitance of payload and switching activity of circuit. Due to the
operating frequency of the device is high, the clock signal is the main factor for
the generation of dynamic power. The paper of Pandey, et al. (2014) shows that
there are no change in DSP power, signal power, logic power if there is a change
in capacitance, but IO power and leakage power are increasing so the overall
power is also increasing. In Pandey, Kumar, Das, Islam and Kumar (2014) the
authors analyse that there is no any change in clock power due to airow, but
the airow is aecting the logic power, signal power, DSPs power and IOs power
and they are increasing. The authors have used 250 LFM and 500LFM airow
in order to design an energy ecient FIR lter. They have used custom, low
prole, medium prole and high prole hit the sink. In Pandey, et al. (2018), FIR
lter is using 5% of IO resource available in ultra–scale FPGA. So, then there is
a possibility to implement bigger FIR lter in this ultra–scale FPGA. FIR lter
is using 1 out of 480 clock buer available on FPGA so then it provides 479
remaining global clock buer to the dierent component of future design. The
distribution of dynamic and static power is 15% and 85% as shown in Figure 2.
Figure 2. Power Dissipation of FIR Filter. Source: Pandey, et al., 2018.
In Pandey, et al. (2017), the author has analysed the power demand by device
of Artix–7, Kintex–7, Zynq and ultrascale FPGA then they conclude that
all programmable SoC is a power hungry architecture but Kintex ultra–
scale architecture is the very energy ecient architecture. There is signicant
improvement when they migrate design from 28 nm process technology based seven
series architecture to 20 nm process technology based ultra–scale architecture.
Reduction in latency will increase the eciency of any communication design
41
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
41
not only this FIR Filter but also many others. The requirement for accurate, high
performance and indoor localization using wireless sensor networks (WSNs) is
increasing day by day (Pak, Ahn, Shmaliy & Lim, 2015). Zhao, Shmaliy, Huang
and Liu (2015) research work is concerned with the minimum variance unbiased
(MVU) nite impulse response (FIR) ltering problem for a linear system. Digital
lters are mainly used in a lot of digital signal processing areas. Filters of nite
impulse response (FIR) category has stability and compliance to be adaptive, in
compare to lters of innite impulse response (IIR) category (Mirghani, 2018).
Transpose form nite–impulse–response (FIR) lters are inherently pipelined
and support multiple constant multiplications (MCM) technique (Mohanty &
Meher, 2016).
3. RESULT AND DISCUSSION
Table 1 has shown the total power consumption of Gaussian low pass FIR lter
for 5 pF capacitance at dierent frequencies. The total power consumption in
Gaussian low pass FIR lter for 5 pF capacitance is 0.072W, 0.125W, 0.153W,
0.291W, 0.566W on 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz respectively.
Table 1. Power of Gaussian Low Pass FIR Filter for 5 pF Capacitance.
Frequency
Dynamic Power
(Watt)
IO–Power
(Watt)
Leakage Power
(Watt)
Total Power
(Watt)
1 GHz 0.017 0.040 0.015 0.072
2 GHz 0.029 0.081 0.015 0.125
2.5 GHz 0.036 0.101 0.016 0.153
5 GHz 0.074 0.201 0.017 0.291
10 GHz 0.144 0.403 0.020 0.566
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
42
Figure 3. Power Dissipation of GLP FIR Filter on a different frequency and 5 pF capacitance.
As we can see, power dissipation is increasing with respect to frequency and
capacitance. The total power is the sum of static and dynamic power, and the
Dynamic Power is the sum of signal, clock, and logic power. The distribution of
power analysis has shown in Figure 3.
Table 2. Power of Gaussian Low Pass FIR Filter for 10 pF Capacitance.
Frequency
Dynamic Power
(Watt)
IO–Power
(Watt)
Leakage Power
(Watt)
Total Power
(Watt)
1 GHz 0.017 0.049 0.015 0.080
2 GHz 0.029 0.097 0.016 0.142
2.5 GHz 0.036 0.121 0.016 0.174
5 GHz 0.074 0.242 0.017 0.333
10 GHz 0.144 0.485 0.021 0.650
Table 2 has shown the total power consumption of Gaussian low pass FIR lter
for 10 pF capacitance at dierent frequencies. The total power consumption in
Gaussian low pass FIR lter for 10 pF capacitance is 0.080W, 0.142W, 0.174W,
0.333W, 0.650W on 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz respectively. So,
we can conclude that the total power is increasing with respect to frequency and
capacitance. The total power is the sum of static and dynamic power, and the
Dynamic Power is the sum of signal, clock, and logic power as shown in Figure 4.
43
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
43
Figure 4. Power Dissipation of GLP FIR Filter on a different frequency and 10 pF capacitance.
Table 3. Power of Gaussian Low Pass FIR Filter for 25 pF Capacitance.
Frequency
Dynamic Power
(Watt)
IO–Power
(Watt)
Leakage Power
(Watt)
Total Power
(Watt)
1 GHz 0.017 0.073 0.015 0.105
2 GHz 0.029 0.146 0.016 0.192
2.5 GHz 0.036 0.183 0.016 0.236
5 GHz 0.074 0.366 0.019 0.458
10 GHz 0.144 0.731 0.025 0.900
Table 3 has shown the total power consumption of Gaussian low pass FIR lter
for 25 pF capacitance at dierent frequencies. The total power consumption in
Gaussian low pass FIR lter for 25 pF capacitance is 0.105W, 0.192W, 0.236W,
0.458W, 0.900W on 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz respectively.
IO–Power is the major contributor in total power dissipation of the FIR lter as
shown in Figure 5.
Figure 5. Power Dissipation of GLP FIR Filter on different frequencies and 25 pF capacitance.
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
44
Table 4. Power of Gaussian Low Pass FIR Filter for 40 pF Capacitance.
Frequency
Dynamic Power
(Watt)
IO–Power
(Watt)
Leakage Power
(Watt)
Total Power
(Watt)
1 GHz 0.017 0.098 0.015 0.130
2 GHz 0.029 0.196 0.017 0.241
2.5 GHz 0.036 0.244 0.017 0.298
5 GHz 0.074 0.489 0.020 0.582
10 GHz 0.144 0.978 0.030 1.151
Table 4 has shown the total power consumption of Gaussian low pass FIR lter
for 40 pF capacitance at dierent frequencies. The total power consumption in
Gaussian low pass FIR lter for 40 pF capacitance is 0.130W, 0.241W, 0.298W,
0.582W, 1.151W on 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz respectively. So,
dynamic power is approx. 13% of total power dissipation and static power is 87%
of total power dissipation for 1 GHz as shown in Figure 6.
Figure 6. Power Dissipation of GLP FIR Filter on different frequencies and 40 pF capacitance.
Table 5. Power of Gaussian Low Pass FIR Filter for 50 pF Capacitance.
Frequency
Dynamic Power
(Watt)
IO–Power
(Watt)
Leakage Power
(Watt)
Total Power
(Watt)
1 GHz 0.017 0.114 0.016 0.147
2 GHz 0.029 0.228 0.017 0.275
2.5 GHz 0.036 0.286 0.018 0.340
5 GHz 0.074 0.571 0.022 0.666
10 GHz 0.144 1.142 0.034 1.320
Table 5 has shown the total power consumption of Gaussian low pass FIR lter
for 50 pF capacitance at dierent frequencies. The total power consumption in
Gaussian low pass FIR lter for 50 pF capacitance is 0.147 W, 0.275 W, 0.340 W,
0.666 W, 1.320 W on 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz respectively. So,
we can say that dynamic power is increasing with respect to frequency. The total
power is the sum of static and dynamic power as shown in Figure 7.
45
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
45
Figure 7. Power Dissipation of GLP FIR Filter on a different frequency and 40 pF capacitance.
Table 6. IO Power analysis of Gaussian Low Pass FIR Filter.
Frequency 5 pF 10 pF 25 pF 40 pF 50 pF
1 GHz 0.040 0.049 0.073 0.098 0.114
2 GHz 0.081 0.097 0.146 0.196 0.228
2.5 GHz 0.101 0.121 0.183 0.244 0.286
5 GHz 0.201 0.242 0.366 0.489 0.571
10 GHz 0.403 0.485 0.731 0.978 1.142
As we can see in Table 6, the IOs power is decreasing by decreasing the device
operating frequency and by decreasing the capacitance values. It is decreasing at
approx. 14%, 35%, 57%, 64% when the capacitance value is scaled down from
50 pF to 40pF, 25pF, 10pF and 5 pF for the all range of frequency, which we have
used for FIR lter i.e. 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz. In another way,
the IOs power is decreasing by 50%, 75%, 80%, 90% when we decrease the FIR
lter device operating frequency from 10 GHz to 5 GHz, 2.5GHz, 2 GHz and 1
GHz for all capacitance values as shown in Figure 8.
Figure 8. IO–Power Dissipation of GLP FIR Filter on the different capacitance value.
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
46
Table 7. Leakage Power analysis of Gaussian Low Pass FIR Filter.
Frequency 5 pF 10 pF 25 pF 40 pF 50 pF
1 GHz 0.015 0.015 0.015 0.015 0.016
2 GHz 0.015 0.016 0.016 0.017 0.017
2.5 GHz 0.016 0.016 0.016 0.017 0.018
5 GHz 0.017 0.017 0.019 0.020 0.022
10 GHz 0.020 0.021 0.025 0.030 0.034
As we can see in Table 7, the Leakage power is decreasing by decreasing the device
operating frequency and by decreasing the capacitance values. It is decreasing at
approx. 6%, 12%, 20% when the capacitance value is scaled down from 50 pF
to 5 pF for 2 GHz to 10 GHz frequency. In another way, the leakage power is
decreasing by 25%, 28%, 40%, 50% and 52% when we decrease the FIR lter
device operating frequency from 10 GHz to 1 GHz for 5 pF, 10 pF, 25 pF, 40 pF,
50 pF capacitance value respectively. This analysis has shown in Figure 9.
Figure 9. IO–Power Dissipation of GLP FIR Filter on the different capacitance value.
Table 8. Total Power analysis of Gaussian Low Pass FIR Filter.
Frequency 5 pF 10 pF 25 pF 40 pF 50 pF
1 GHz 0.072 0.080 0.105 0.130 0.147
2 GHz 0.125 0.142 0.192 0.241 0.275
2.5 GHz 0.153 0.174 0.236 0.298 0.340
5 GHz 0.291 0.333 0.458 0.582 0.666
10 GHz 0.566 0.650 0.900 1.151 1.320
As we can see in Table 8, the total power is decreasing by decreasing the device
operating frequency and by decreasing the capacitance values. It is decreasing at
approx. 12%, 30%, 48%, 57% when the capacitance value is scale down from
50 pF to 40pF, 25pF, 10pF and 5 pF respectively. In another way, the total power
is approx. 88% decreasing when we decrease the FIR lter device operating
47
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
47
frequency from 10 GHz to 1 GHz as shown in Figure 10.
Figure 10. IO–Power Dissipation of GLP FIR Filter on the different capacitance value.
4. CONCLUSION
According to the above analysis, we have analysed dynamic power are increasing
due to change in device operating frequency but for the same frequency, the
dynamic power remains the same for any value of capacitance. Instead of this, the
IO power, leakage power is increasing if we use capacitance scaling techniques as
well as scaling of device operating frequency. The IO power is decreasing approx.
14%, 35%, 57%, 64% when the capacitance value is scaled down from 50 pF to
40pF, 25pF, 10pF and 5 pF for the all range of frequency, which we have used
for FIR lter i.e. 1 GHz, 2 GHz, 2.5 GHz, 5 GHz, 10 GHz. The leakage power
is decreasing approx. 6%, 12%, 20% when the capacitance value is scaled down
from 50 pF to 5 pF for 2 GHz to 10 GHz frequency. But here we can say that the
leakage power is increasing very slowly with increasing capacitance. The total
power is decreasing approx. 12%, 30%, 48%, 57% when the capacitance value
is scale down from 50 pF to 40pF, 25pF, 10pF and 5 pF respectively. In another
way, the total power is 88% and 50% decreasing when we decrease the FIR lter
device operating frequency from 10 GHz to 1 GHz and 5 GHz respectively.
3C Tecnología. Glosas de innovación aplicadas a la pyme. ISSN: 2254–4143
48
5. FUTURE SCOPE
In this paper, we have used the Spartan–6 FPGA to design the energy ecient
Gaussian low pass lter. There are many open scopes available to make the
energy ecient lter design using Floating–Point, Modulation, Transforms,
Demodulation, Video, Error Correction, Imaging and even more DSP IP block.
The current FPGA which we have used in this paper is 45nm FPGA. There is
open scope to implement the design on 28nm FPGA, 20nm or even lower 14nm
ultra–scale FPGA.
49
Edición Especial Special Issue Mayo 2019
DOI: http://dx.doi.org/10.17993/3ctecno.2019.specialissue2.36-49
49
REFERENCES
Mirghani, M. (2018). Analysis of Successive Coecients FIR Filter. In 2018
International Conference on Computer, Control, Electrical, and Electronics Engineering
(ICCCEEE), pp. 1–4. IEEE.
Mohanty, B. K. & Meher, P. K. (2016). A high–performance FIR lter
architecture for xed and recongurable applications. IEEE transactions on very
large scale integration (VLSI) systems, 24(2), pp. 444–452.
Pak, J. M, Ahn, C. K., Shmaliy, Y. S., & Lim, M. T. (2015). Improving
reliability of particle lter–based localization in wireless sensor networks via
hybrid particle/FIR ltering. IEEE Transactions on Industrial Informatics, 11(5),
pp. 1089–1098.
Pandey, B., Das, B., Kaur, A., Kumar, T., Khan, A. M., Akbar Hussain,
D. M. & Tomar, G. S. (2017). Performance Evaluation of FIR Filter
After Implementation on Dierent FPGA and SOC and Its Utilization in
Communication and Network. Wireless Personal Communication, 95(2), pp. 375–
389.
Pandey, B., Kumar, T., Das, T., Islam, S. M. M. & Kumar, J. (2014).
Thermal Mechanics Based Energy Ecient FIR Filter for Digital Signal
Processing. Applied Mechanics and Materials, 612, pp. 65–70. doi: http://dx.doi.
org/10.4028/www.scientic.net/AMM.612.65
Pandey, B., Kumar, T., Das, T., Yadav, R. & O. J. Pandey. (2014). Capacitance
Scaling Based Energy Ecient FIR Filter (ICROIT), MRIU, Faridabad, 6–8.
Pandey, B., Pandey, N., Kaur, A., Hussain, D. M. A., Das, B. & Tomar, G.
S. (2018). Scaling of Output Load in Energy Ecient FIR Filter for Green
Communication on Ultra–Scale FPGA, Wireless Personal Communication.
Available in https://link.springer.com/article/10.1007/s11277–018–5717–2
Zhao, S., Shmaliy, Y. S., Huang, B., & Liu, F. (2015). Minimum variance
unbiased FIR lter for discrete time–variant systems. Automatica, 53, pp. 355–
361.
